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Ⅰ. 插件描述

Verilog HDL/SystemVerilog HDVL indent file

Ⅱ. 基本信息

创建日期：  2007-12-12 使用用户：  6 Github星：  2 插件作者：  MingZhi Li

Ⅲ. 安装方法

使用Vundle管理器安装

在你的.vimrc下添加:

Plugin '/verilog-vim-who-speaks'

… 然后在Vim中运行以下命令:

:source %
:PluginInstall

对于Vundle版本 < 0.10.2，请用上面的Bundle替换Plugin。

使用NeoBundle管理器安装

在你的.vimrc下添加:

NeoBundle '/verilog-vim-who-speaks'

… 然后在Vim中运行以下命令:

:source %
:NeoBundleInstall

使用VimPlug管理器安装

在你的.vimrc下添加:

Plug '/verilog-vim-who-speaks'

… 然后在Vim中运行以下命令:

:source %
:PlugInstall

使用Pathogen管理器安装

在终端中运行以下命令:

cd ~/.vim/bundle
git clone https://github.com/vim-scripts/verilog.vim

Ⅳ. 文档说明

" Title:        Verilog HDL/SystemVerilog HDVL indent file
" Maintainer: Mingzhi Li <limingzhi05@mail.nankai.edu.cn>
" Last Change: 2007-12-16 20:10:57 CST
"
" Buffer Variables:
"     b:verilog_indent_width   : indenting width(default value: shiftwidth)
"
" Install:
"     Drop it to ~/.vim/indent
"
" URL:
"    http://www.vim.org/scripts/script.php?script_id=2091
"
" Revision Comments:
"     Mingzhi Li  2007-12-16 20:09:39 CST Version 1.2      
"        Bug fixes
"     Mingzhi Li  2007-12-13 23:47:54 CST Version 1.1      
"        Bug fix, improve performance and add introductions
"     Mingzhi Li  2007-12-7  22:16:41 CST Version 1.0  
"        Initial version
"      
" Known Limited:
"     This indent file can not work well, when you break the long line into
"     multi-line manually, such as:
"      always @(posedge a or posedge b
"          or posedge c ) begin
"         //...
"      end
"     Recommend to use the coding style(wraped by vim automatically) as following:
"       always @(posedge a or posedge b or posedge c ) begin
"         //...
"       end